This invention relates generally to digital clocks for appliances (e.g., microwave ovens, ranges, and video cassette recorders) and more particularly, to apparatus and methods for controlling such digital clocks so that upon the occurrence of a short power outage, the clock may continue to operate upon restoration of power without requiring manual resetting.
Microwave ovens, ranges, video cassette recorders, and many other appliances include a digital clock which displays the time of day. Power for the clock typically is obtained from the AC power line which supplies power to other appliance components. If the AC power is lost, even for a brief instant, the clock must be manually reset. Although having to reset the clock is not necessarily difficult or time consuming, it can be a nuisance.
It would be desirable to provide an appliance incorporating a digital clock which is tolerant to short power outages so that the clock does not necessarily need to be reset manually after a brief, e.g., 20-30 seconds, power outage. It also would be desirable to provide such a clock which has generally acceptable accuracy and does not add significant costs to the appliance.
These and other objects may be attained by clock saver apparatus and methods which enable the restoration of clock operations in the event that a power outage is brief and without requiring that an operator reset the clock. In one embodiment, the clock is restored to a time setting equal to the time at which the power outage was detected. For example, if the power outage is detected at 11:08:32 a.m., then the restored time after restoration of power is set at 11:08:32 a.m. In another embodiment, the clock is restored to a time setting equal to the time at which the power outage was detected plus the determined time duration of the power outage. For example, if the power outage is detected at 11:08:32 a.m., and if the power outage duration is 15 seconds, then the restored time after restoration of power is set at 11:08:47 a.m.
In an exemplary embodiment, the apparatus includes a microprocessor, a non-volatile memory coupled to the microprocessor, a user interface (e.g., a keypad and display) coupled to the microprocessor, and a time determining circuit coupled to the microprocessor for measuring an elapsed time from loss of power and restoration of power. The microprocessor includes a first port normally set to high during microprocessor operations. The microprocessor further includes a second port and an on-board analog to digital converter. The second port is coupled to the converter. The microprocessor also includes a power failure detection timer, and the power failure detection timer is reset once per line cycle. As is well known, there are sixty line cycles per second in a 60 Hz AC system.
The power outage time determining circuit includes a capacitor coupled to the first port of the microprocessor for receiving a charge during microprocessor operations. The capacitor also is coupled to the microprocessor second port so that a signal representative of the remaining charge stored in the capacitor is supplied to the second port.
In the above described embodiment, the microprocessor firmware controls operations of the microprocessor to perform the clock saver operations. Specifically, the microprocessor detects a predetermined condition associated with a power outage, and upon detection of the predetermined condition, the microprocessor stores clock data in the non-volatile memory. In the exemplary embodiment, the predetermined condition associated with the power outage is that a predetermined number (e.g., 3 or more) of AC line cycles have elapsed since resetting the power failure detection timer.
Upon restoration of power, the microprocessor determines whether the power outage duration was less than a predetermined time period. Particularly, the microprocessor determines the magnitude of the charge representative signal from the power outage time determining circuit. If the determined signal magnitude is greater than the predetermined value, then the power outage duration was shorter than the predetermined time period. If the determined signal magnitude is equal to or less than the predetermined value, then the power outage duration was longer than the predetermined time period.
If the power outage duration was less than the predetermined time period, the microprocessor restores clock operations using the stored clock data. Specifically, the microprocessor reads the stored clock data from the non-volatile memory and sets the clock using the read data. As explained above and in one embodiment, the clock is restored to a time setting equal to the time at which the power outage was detected. In another embodiment, the clock is restored to a time setting equal to the time at which the power outage was detected plus the determined time duration of the power outage.
The above described clock saver apparatus provides the desirable result that the appliance digital clock is tolerant to short power outages so that the clock does not necessarily need to be reset after a brief, e.g., 20-30 seconds, power outage. Even without adjusting the clock setting for the duration of the power outage, which is contemplated and possible as described above, the clock saver apparatus provides sufficient accuracy for most users and does not add significant costs to the appliance.